Looking for JTAG Cable? Learn about various JTAG pinouts. Unfortunately there is no standard JTAG pinout. Usually the JTAG connector is a simple two row header on a center-line with 0.1 inches pin-to-pin spacing.

This page lists pinouts for common JTAG connectors. You can use this information to help you create custom JTAG cable or to connect your JTAG hardware to existing JTAG interface.

There are many JTAG header arrangements, from 10-pin to 20-pin headers. If you are designing with ARM or MIPS microprocessor, we recommend using appropriate JTAG connector (EJTAG or ARM JTAG) to maintain compatibility with development tools. In other cases we recommend you using JTAG connector for manufacturer of your part or AVR/Byteblaster JTAG (which is compatible with many other products) or standard 8 pin "PLD" JTAG connector.

Daisy chaining multiple devices

If your design uses multiple devices with JTAG TAP, you must either use separate connector for each device or chain devices. Generally, JTAG supports many devices in single JTAG chain, but many tools are not compatible with this feature. Check tool's documentation before you put devices into chain.

Interface Signals

The JTAG interface, also known as a Test Access Port, or TAP, uses the following five signals to support the operation of the boundary scan:

TCK – the TCK or 'test clock' synchronizes the internal state operations of the machine TMS – the TMS or 'test mode state' determines the next state and is sampled at the rising edge of TCK TDI – the TDI or 'test data in' is sampled at the rising edge of TCK signal when the internal state machine is in the correct state and represents the data shifted into the device's test or programming logic. TDO – the TDO or 'test data out' is valid on the falling edge of TCK when the internal state machine is in the correct state and represents the data shifted out of the device's test or programming logic. TRST – the TRST or 'test reset' is an optional pin which, when available, can reset the TAP controller's state machine.

8 Pin PLD-JTAG JTAG pinout

1 VCC pin
2 TDO pin
3 TDI pin
4 nSRST pin
5
6 TMS pin
7 GND pin
8 TCK pin

 

10 Pin AVR JTAG pinout

1 TCK pin pin GND 2
3 TDO pin pin VREF 4
5 TMS pin pin nSRST 6
7 - pin pin nTRST 8
9 TDI pin pin GND 10

 

10 Pin Altera ByteBlaster JTAG pinout

1 TCK pin pin GND 2
3 TDO pin pin VREF 4
5 TMS pin pin - 6
7 - pin pin - 8
9 TDI pin pin GND 10

 

10 Pin Maxim MAXQ JTAG header pinout

1 TCK pin pin GND 2
3 TDO pin pin VREF 4
5 TMS pin pin nSRST 6
7 - pin pin VSUPPLY 8
9 TDI pin pin GND 10

 

10 Pin Actel FlashPro JTAG pinout

1 TCK pin pin GND 2
3 TDO pin pin - 4
5 TMS pin pin VJTAG 6
7 VPUMP pin pin TRST 8
9 TDI pin pin GND 10

 

10 Pin Cypress Ultra ISR JTAG pinout

1 GND pin pin TMS 2
3 JTAGEN pin pin TCK 4
5 ISR pin pin TDI 6
7 VREF pin 8
9 TDO pin pin GND 10

 

10 Pin Lattice JTAG pinout

1 TCK pin pin - 2
3 TMS pin pin GND 4
5 TDI pin pin VREF 6
7 TDO pin pin GND 8
9 nTRST pin pin nISPEN 10

 

9 Pin Lattice ispDOWNLOAD USB cable JTAG Header pinout

1 VCC pin
2 TDO pin
3 TDI pin
4 ispEN# pin
5 nTRST pin
6 TMS pin
7 GND pin
8 TCK pin
9 - pin

 

12 Pin JTAG pinout

Found in Linksys routers such as the WRT54G and WRT54GS, the 12-pin header has the following arrangement of JTAG signals and pins:

1 nTRST pin pin GND 2
3 TDI pin pin GND 4
5 TDO pin pin GND 6
7 TMS pin pin GND 8
9 TCK pin pin GND 10
11 nSRST pin pin GND 12

Seems, this header is a truncated version of the full EJTAG header.

14 Pin JTAG Header

This header is fully MIPS EJTAG 2.6 compatible and described in the EJTAG 2.6 standard. Found in Edimax routers (and other mostly embedded devices, including on many WiFi devices), the 14-pin header has the following arrangement of JTAG signals and pins:

1 nTRST pin pin GND 2
3 TDI pin pin GND 4
5 TDO pin pin GND 6
7 TMS pin pin GND 8
9 TCK pin pin GND 10
11 nSRST pin pin n/a 12
13 n/a pin pin Vcc 14

 

A buffered JTAG cable such as the Wiggler requires an external Vcc voltage supply. The 14-pin header conveniently supplies this voltage on pin 14. The typical unbuffered JTAG cable, however, does not require an external voltage in order to function. Formally, the pin 14 is called VREF and used to indicate a JTAG signal levels: 5V, 3.3V or 2.5V. On the most devices this pin is tied to the device's Vcc and may be used to power a buffer IC chip (and to generate an appropriate levels as result). Note that the 12-pin JTAG header arrangement does not provide Vcc.

14 Pin ARM JTAG Header

1 VREF pin pin GND 2
3 nTRST pin pin GND 4
5 TDI pin pin GND 6
7 TMS pin pin GND 8
9 TCK pin pin GND 10
11 TDO pin pin nSRST 12
13 VREF pin pin GND 14

14 Pin Texas Instruments MSP430 JTAG pinout

1 TDO pin pin VREF 2
3 TDI pin pin - 4
5 TMS pin pin TCLK 6
7 TCK pin pin VPP 8
9 GND pin pin - 10
11 nSRST pin pin - 12
13 - pin pin - 14

9 Pin Xilinx Parallel III and IV JTAG pinout

1 VREF pin
2 GND pin
3 - pin
4 TCLK pin
5 - pin
6 TDO pin
7 TDI pin
8 - pin
9 TMS pin

14 Pin Xilinx Parallel IV JTAG Header pinout

1 VGND pin pin VREF 2
3 GND pin pin TMS 4
5 GND pin pin TCK 6
7 GND pin pin TDO 8
9 GND pin pin TDI 10
11 GND pin pin - 12
13 GND pin pin - 14

20 Pin Toshiba MIPS JTAG header

1 nTRST pin pin - 2
3 TDI pin pin GND 4
5 TDO pin pin GND 6
7 TMS pin pin GND 8
9 TCK pin pin GND 10
11 VREF pin pin GND 12
13 nSRST pin pin - 14
15 - pin pin - 16
17 - pin pin - 18
19 - pin pin - 20

 

20 Pin Philips MIPS JTAG header pinout

1 nTRST pin pin GND 2
3 TDI pin pin GND 4
5 TDO pin pin GND 6
7 TMS pin pin GND 8
9 TCK pin pin GND 10
11 nSRST pin pin GND 12
13 - pin pin GND 14
15 - pin pin GND 16
17 - pin pin GND 18
19 - pin pin GND 20

 

20 Pin ARM JTAG Header

Used with almost all ARM-based microcontrollers.

1 VREF pin pin VSUPPLY 2
3 nTRST pin pin GND 4
5 TDI pin pin GND 6
7 TMS pin pin GND 8
9 TCK pin pin GND 10
11 RTCK pin pin GND 12
13 TDO pin pin GND 14
15 nSRST pin pin GND 16
17 DBGRQ pin pin GND 18
19 DGBACK pin pin GND 20

Registers

Boundary scan has two types of registers: one instruction register and two or more data registers.

Instruction Register – the instruction register holds the current instruction. Its content is used by the test access port (TAP) controller to decide what to do with signals that are received. Most commonly, the content of the instruction register will define to which of the data registers signals should be passed.

Data Registers – there are three primary data registers, the Boundary Scan Register (BSR), the BYPASS register and the IDCODES register. Other data registers may be present, but they are not required as part of the JTAG standard.

  • BSR this is the main testing data register. This register is used to move data to and from the device.
  • BYPASS – this is a single-bit register that passes information from TDI to TDO. It allows other devices in a circuit to be tested with minimal overhead.
  • IDCODES – this register contains the ID code and revision number for the device. This information allows the device to be linked to its Boundary Scan Description Language (BSDL) file. The file contains details of the Boundary Scan configuration for the device.

Test Access Port (TAP) Controller

This controller is a state machine which is controlled by the TMS signal. TAP controller controls the behavior of the JTAG system.

All states of the TAP controller state machine have two exits, so all transitions can be controlled by the single TMS signal sampled on TCK.

The two main paths allow for setting or retrieving information from either a data register or the instruction register on the device. The data register operated on (e.g. BSR, IDCODES, BYPASS) depends on the value loaded into the instruction register. A more detailed description of the states of the TAP controller state machine is unfortunately beyond the scope of this brief JTAG tutorial - please refer to the IEEE 1149.1 Standard JTAG document.

Boundary Scan Instructions

These instructions, as defined by the IEEE 1149.1 standard, must be available for a device to be considered compliant:

BYPASS – the BYPASS instruction causes the TDI and TDO lines to be connected via a single-bit pass-through register (the BYPASS register). This instruction allows the testing of other devices in the JTAG chain without any unnecessary overhead.

EXTEST – the EXTEST instruction causes the TDI and TDO to be connected to the Boundary Scan Register (BSR). The device's pin states are sampled with the 'capture dr' JTAG state and new values are shifted into the BSR with the 'shift dr' state; these values are then applied to the pins of the device using the 'update dr' state.

SAMPLE/PRELOAD – the SAMPLE/PRELOAD instruction causes the TDI and TDO to be connected to the BSR. However, the device is left in its normal functional mode. During this instruction, the BSR can be accessed by a data scan operation to take a sample of the functional data entering and leaving the device. The instruction is also used to preload test data into the BSR prior to loading an EXTEST instruction.

Other commonly available instructions include:

IDCODE – the IDCODE instruction causes the TDI and TDO to be connected to the IDCODE register.

INTEST – the INTEST instruction causes the TDI and TDO lines to be connected to the Boundary Scan Register (BSR). While the EXTEST instruction allows the user to set and read pin states, the INTEST instruction relates to the core-logic signals of a device.

A more detailed description of the boundary scan instructions is unfortunately beyond the scope of this brief JTAG pinout description - please refer to the IEEE 1149.1 Standard JTAG document.