JTAG Tutorial - Understand JTAG Cables
In this boundary-scan and JTAG tutorial, you will learn the basic elements of boundary-scan architecture — where it came from, what problem it solves, and the implications on the design of an integrated-circuit device.
This brief JTAG tutorial describes a history of the JTAG, IEEE 1149.1 standard, the boundary scan principle, interface signals, registers, test access port controller, and boundary scan instructions.
Silicon designs have advanced to a level where device density and BGA packaging contributed to the reduced efficiency of traditional testing methods. To overcome this problem a few manufacturers joined into a Joint Test Action Group. This group published findings and some recommendations which were used at the Institute of Electrical and Electronic Engineers (IEEE) standard 1149.1 with the name Standard Test Access Port and Boundary Scan Architecture. This standard has retained its link to the group and is commonly know by the acronym JTAG.The IEEE 1149.1 boundary-scan standard was developed almost 15 years ago to resolve the problems associated with limited physical access for probing test points on pc boards and to verify that device pins have been soldered correctly and are free of solder shorts and open circuits. However, the test industry now faces new problems that nobody envisioned when the standard was developed back in 1990, and a number of working groups have engaged in a sustained effort to develop new standards that build on the success and acceptance of IEEE 1149.1.
More recent standards that extend 1149.1 are 1149.4, the mixed-signal test-bus standard for testing analog pins; 1149.6 for testing the interconnections between AC coupled differential nets; and IEEE 1532 for the in-system configuration of programmable devices. These standards are not covered in this JTAG tutorial.
Boundary scan technology offers the ability to set and read the values on inp>IEEE 1149.1 Standard JTAG document.
The Joint Test Action Group (JTAG) interface is aimed at testing complex logical circuits installed in the device. This interface is described in the IEEE1149.1 Boundary Scan Architecture standard and is of synchronous parallel type; however, because of its specific objective, it differs substantially from the interfaces described above, which are primarily oriented at data transfer. The JTAG interface is controlled by only one controller device (most often, this is a PC with an appropriate interface adapter), to which several devices being tested can be connected. Below are listed JTAG interface signals:
These regular logical level signals (all unidirectional) form the Test Access Port (TAP), via which the device being tested is connected to the test equipment (the controller). The task of the test equipment consists of generating test signals in accordance with the test program defined by the developer of the device being tested, and comparing the obtained results with the template signals. The same controller and port can be used to test any number of devices that support JTAG. For this, the devices are connected in chain by their TAPs. The standardized logic format allows the controller to communicate independently with each device in the chain (for this, they must have working JTAG cells, of course).
The B/S test cells are inserted between the actual external outputs of the device and the logical device proper (i.e., are located on the logical boundary of the device). A TAP controller can scan the cells (i.e., control them and read information from them), hence the name: Boundary Scan. When the test mode is on, the TAP controller can logically disconnect signals from the external outputs, set input actions, and read out the results: Basically, this is all that is necessary to test serial circuits (automatons with memory). The lovely part of the JTAG is that regardless of how complex a device may be, only four signals are used to test it: All the complexities are hidden in the relatively simple cells enveloping its signal outputs.
The testing logic built into a JTAG supporting device consists of the following elements:
The instruction and data registers are separate shift registers connected in parallel. The TDI signal is placed on their inputs and the TDO signal is taken off their outputs. Data are moved one bit for each positive transition.
The BPR register is 1 bit long. It is used as the shortest bypass for the serial data when the rest of the registers are not engaged in the exchange.
The BSR register is a long shift register whose bits are boundary cells placed at each input and output signal of the processor. For bidirectional signal (or their groups), there are control cells that set the operation mode of the information cells, in addition to the register information cells proper corresponding to the external signals. For example, the BSR register for P6 processors is 159 bits long.
The 32-bit DID register holds the manufacturer identifier, device code, and the version number, by which the TAP controller can determine the device, with which it is dealing.
The IR register is used to store the executed test instruction. Its length depends on the device being tested. The instructions BYPASS, IDCODE, SAMPLE, and EXTEST are mandatory for all devices.
The BYPASS instruction (all code bits are 1) is intended for connecting a 1-bit bypass register, providing data the fastest path through the device; at this, the device does not react to the transiting data flow. The TDI line is usually pulled by a resistor to the high level, so that breaking a JTAG chain will connect the bypass registers in all devices after the break point. This excludes potentially unpredictable device behavior in case of a chain break.
The IDCODE identification instruction (two least significant bits of the code are set to 10) connects the DID register to the interface, making it possible to read its contents (incoming input data cannot change its value).
The SAMPLE/PRELOAD instruction (two least significant code bits are 01) has two functions. When the TAP controller is in the Capture-DR state, this instruction allows a snapshot of all external signals to be taken without affecting the device's operation. Signals' values are latched at the positive TCK transition. In the Update-DR state, this instruction loads data into the output cells of the test port (but not to the device's outputs yet), from where they will be subsequently placed onto the processor's outputs by the EXTEST instruction. Data are loaded at the negative transition of the TCK signal.
The EXTEST instruction (two least significant bits of its code are 00) is used to test external (with respect to the device being tested) circuits. In this operation, signals written in advance to the BSR register are placed on the outputs, while the state of the input signals is latched in these registers. Bidirectional signals are configured beforehand by their corresponding bits of the BSR cells.
The 1149.1 standard also provides the INTEST instruction for testing internal logic of devices, but not all devices support it.
The TAP controller is a synchronous finite automaton that changes its state at the positive transition of the TCK signal and upon power up. Change of states is controlled by the TMS (Test Mode State) signal, which is clocked by the positive transition of the TCK signal.
The controller returns to the initial Test-Logic-Reset state automatically upon power up. From any other state, it can be returned to the initial state by the high-level TMS signal held for at least five TCK cycles. Sometimes, the controller can also be placed into the initial state by the optional TRST signal. In this state, the test logic is disabled, and the device works in the regular mode.
The Run-Test/Idle state is an intermediate state between test operation executions. In this state, the registers' values do not change.
While in the Capture-DR state, during execution of the EXTEST and SAMPLE/PRELOAD instructions, the scanning register only latches data on the input lines.
In the Shift-DR state, data from the TDI move via the connected shift register to the TDO output.
In the Pause-DR state, the controller temporarily disables data movement via the shift register.
In the Update-DR state, signals from the shift register are latched on the outputs of the test cells at the TCK fall.
In the Capture-IR state, the controller loads the code of the SAMPLE instruction into the shift register.
In the Shift-IR state, an instruction shift register is inserted into the chain between the TDI and TDO, but the previous instruction is still being executed.
In the Pause-IR state, the controller temporarily disables data movement through the instruction shift register.
In the Update-IR state, a new instruction to be executed is latched at the fall of the TCK signal and its corresponding register is inserted into the TDI-TDO chain.
In addition to these main controller states, which determine the actions of the test equipment, there also are temporary intermediate states necessary to implement automaton's transitions. To these belong the Select-DR-Scan, Exit1-DR, Exit2-DR, Select-DR-Scan, Exit1-IR, and Exit2-IR states.
A special Boundary Scan Description Language (BSDL) has been developed for the JTAG interface to describe devices. The make-up and sequence order of the information and control cells in the data shift register is specific to each device (that's what the identification register is for), and is provided by the device's developers.
The JTAG interface is used not only for testing but also for programming various devices, including nonvolatile microcontroller memory. The PCI bus has contacts for the JTAG signals. However, their usage is not uniform: They are either left unused or are chained up. Modern processors are equipped with the JTAG interface, making it possible not only to test the processor itself (which operation has no application interest) but also to organize probe-mode debugging. The probe mode is a powerful means of system software debugging; a usual processor linked with a test controller by the JTAG interface turns into an in-circuit emulator—every system-software developer's dream.In this Jtag tutorial, we have presented the history of the standard, the architecture of an IEEE 1149.1-compliant device, and a simple introduction to the boundary scan architecture. For further details on boundary-scan please check the IEEE 1149.1 Standard.
Obtaining the IEEE 1149.1 Standard
The IEEE 1149.1 Standard JTAG specification is available directly from IEEE:
IEEE Standards Department 445 Hoes Lane P.O. Box 1331 Piscataway, NJ 08855-1331 USA